Skills
Static Timing Analysis (STA)
Timing Closure
ASIC/SoC Physical Design
About the Role
Astera Labs is seeking a Principal Physical Design Engineer focused on Static Timing Analysis (STA). In this role, you will help ensure high-performance, reliable operation of complex semiconductor designs that support rack-scale AI infrastructure and advanced connectivity technologies.
Responsibilities
- Own and drive STA methodology across design blocks and full-chip flows
- Analyze timing reports, identify root causes, and recommend corrective actions
- Collaborate with physical design, verification, and architecture teams to achieve timing closure
- Develop and maintain scripts and automation to improve analysis quality and turnaround time
- Review constraints and timing models to ensure accuracy across process, voltage, and temperature corners
- Support sign-off readiness by validating timing coverage and documenting results
Requirements
- Strong experience with static timing analysis and timing closure for advanced ASIC/SoC designs
- Proficiency with industry-standard STA tools and workflows
- Deep understanding of timing constraints, clocks, CDC considerations, and corner/constraint management
- Experience debugging timing issues using logs, reports, and design knowledge
- Strong scripting skills (e.g., Python/Tcl or similar) for flow automation
- Excellent collaboration skills across cross-functional engineering teams
Benefits
- Opportunity to work on cutting-edge AI infrastructure technologies
- Collaborative, high-impact engineering environment
- Competitive compensation and benefits package
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