Skills
Place and Route
Timing Closure
ASIC Physical Design
About the Role
Astera Labs is building rack-scale AI infrastructure with connectivity solutions that help organizations scale modern AI systems. In this Physical Design Engineer (Place & Route) role, you will support the planning and implementation of advanced chip designs, partnering with engineering teams to achieve timing, power, and quality targets.
Responsibilities
- Drive place-and-route implementation from planning through signoff for complex designs
- Develop and refine physical design flows, constraints, and scripts to improve convergence
- Analyze timing, congestion, and power results, then iterate to meet design goals
- Collaborate with RTL, verification, and architecture teams to resolve physical design challenges
- Support verification and signoff activities, including documentation of implementation outcomes
Requirements
- Experience with ASIC physical design, specifically place-and-route
- Strong understanding of timing closure, congestion analysis, and constraint management
- Proficiency with industry-standard EDA tools and scripting for flow automation
- Ability to troubleshoot implementation issues and guide design iterations effectively
Benefits
- Work on cutting-edge AI infrastructure technology
- Collaborate with a team focused on high-impact engineering
- Opportunity to grow expertise in advanced physical design methodologies
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