Skills
Physical design
Timing closure
EDA tools
About the Role
Astera Labs is seeking a Senior/Staff Physical Design Engineer to help design high-performance semiconductor connectivity solutions. In this role, you will own key aspects of the physical design flow, ensuring layouts meet stringent timing, power, and area targets for advanced hardware platforms.
Responsibilities
- Lead physical design planning and implementation from floorplan through signoff
- Own timing closure strategy, including constraint development and iterative optimization
- Drive detailed analysis of routing, congestion, and manufacturability concerns
- Collaborate with RTL/logic, verification, and system teams to resolve integration challenges
- Support DRC/LVS readiness and coordinate signoff activities to meet release requirements
Requirements
- Proven experience in physical design (e.g., placement, routing, timing closure) for complex SoC/ASIC designs
- Strong understanding of timing analysis, constraints, and optimization techniques
- Experience with industry-standard EDA tools and workflows
- Ability to troubleshoot complex layout and timing issues using data-driven approaches
- Strong communication skills for cross-functional collaboration
Benefits
- Opportunity to work on cutting-edge AI infrastructure technologies
- Collaborative, high-impact engineering environment
- Competitive compensation and benefits package (details provided during the hiring process)
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