Skills
Silicon verification
SystemVerilog
UVM
About the Role
Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team builds the foundational technologies that power the company’s “Intelligent Cloud” mission. Within SCHIE, the Compute Silicon & Manufacturing Engineering (CSME) organization drives the design, development, manufacturing, and packaging of Microsoft’s next-generation computer chips.
We are seeking a Principal Silicon Design Verification Engineer to help ensure our silicon platforms meet performance, reliability, and quality goals before they reach manufacturing and deployment.
Responsibilities
- Develop and execute verification strategies for complex silicon designs across multiple stages of the design lifecycle
- Create, extend, and maintain verification environments, testbenches, and automation to improve coverage and productivity
- Drive functional verification efforts, including writing directed and constrained-random tests and improving coverage closure
- Collaborate with design, architecture, and manufacturing teams to debug issues and validate fixes
- Perform root-cause analysis for silicon/verification escapes and implement process improvements
- Mentor engineers and partner with cross-functional teams to raise verification standards
Requirements
- Strong background in hardware verification for ASICs or similar silicon platforms
- Proficiency with verification methodologies and tools (e.g., SystemVerilog/UVM and related ecosystems)
- Experience building scalable testbenches, coverage models, and automation for verification workflows
- Solid debugging skills using simulation and/or formal techniques
- Ability to collaborate effectively across engineering disciplines and communicate technical findings clearly
Benefits
- Opportunity to work on cutting-edge silicon that powers Microsoft cloud services and products
- Collaborative, high-impact engineering environment
- Professional growth through mentorship and cross-team technical collaboration
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